laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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Add support for literal pool in Addressing module

laforest opened this issue · comments

Currently, Addressing selects a default offset of zero if the instruction operand points to an I/O port or to High Memory.

We should add another Address_Decoder to OR with the default offset selector to also enable direct access to a small region of memory to hold common (usually read-only) data: a literal pool, which would hold common values (0, 1, -1, 2^N, etc...), tables of coefficients, etc... used by all threads.

Really it's a shared, directly-addressed memory area for all threads. It would be a good place for mailboxes/semaphores/mutexes, etc...