laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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Extend D address space +2 bits

laforest opened this issue · comments

Extending the D operand +2 bits (to 12 bits in vanilla 36-bit configuration), and reconfiguring the write enables of the A/B/I memories, would eliminate data and code duplication across all memories, by enabling at compile time to control where ALU results get written.

Assuming all the memories are identical (1024 words), we can arrange them thus in the D address space:

0-1023: A
1024 - 2047: B
2048 - 3071: I
3072 - 4095: H (call it "high mem", as a DOS homage? ;) )

The A and B operands still read the A/B memories, and the PC reads the I memory, and all remain at 10 bits and index from 0. The D operand of branches now wraps around I memory 4 times, or put another way, ignores the two upper bits.

Thus, as-is, the H memory is write-only and a good place to put hardware extensions which aren't interactive. This reduces the number of A and B I/O ports needed.

Finally, this scheme won't work for word widths without 2 free instruction bits, but supporting all possible word widths (without modification) has lost importance. It was enough to prove that all word widths were usable and fast.

Supersedes #3, closed by same commit 179d46f