laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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Add write-enable bits in the instruction format

laforest opened this issue · comments

Add Jason & Matthew's proposal to use the last 2 bits in the 36-bit instruction format to control the write-enable lines for the I/A/B memories to eliminate the need to duplicate all code and data across all three memories.

For larger widths, instead of finding the special cases where 2 spare bits remain, we could limit the address space by stealing bits from the D/A/B operand fields. Enough range will remain in practice, and we can get more than 2 bits this way if needed.

Fixed around commit 179d46f, by which time there was basic (new) assembler support.

The actual solution was to extend the Destination operand from 10 to 12 bits, allowing us to map A/B/I memories in that order at base write addresses 0/1024/2048, with the last 1024 words being H ("High") memory, write-only, where we can place control registers for later hardware extensions.

Thus we eliminate data and instruction memory duplication. :)

Actually superseded by #30, also closed.