laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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Place instruction annulling logic in a module

laforest opened this issue · comments

Currently, it litters the RTL diagram with per-wire AND gates, making the diagrams harder to read. This new module would have an instance in the Control and Data paths.