laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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Cancel *all* read and write handshakes if *any* are not ready

laforest opened this issue · comments

In the worst case, an instruction will read from 2 I/O ports (or twice simultaneously from the same port!), and write to an I/O port (which may be at the same address as one of the read port). The instruction will raise req on each of these ports to signal the other end that the handshake may complete.

However, if any of the ports cannot complete the handshake (low ack), then no port should raise req (or let a raised req get to the other end), because if the handshake were to complete, the data would be lost since the instruction will be annulled anyway.

This will be a tricky one to implement without impacting Fmax, as by itself, it implies a loop going from remote req to local ack back out via local req then back to remote ack, meaning double the normal propagation delay between ends. Also, it requires interconnecting all I/O port hardware, across both A and B memories.

Do this one after #21 and #22 are done.