laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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Annul instruction if the I/O write handshake not ready

laforest opened this issue · comments

At the time of checking the ack lines for both reads (in RD0), do the same for the write port: in WR0, select the correct ack line and use it to annul an instruction before it reaches the Controller and ALU.

Given a completed #21, this should implement in a similar way, and can just tack on to the existing muxing and annulling circuitry.