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laforest / Octavo

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Home Page:http://fpgacpu.ca/

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Convert wren/rden signals to req/ack form

laforest opened this issue · comments

commented

There are several ways to label the signals of a 4-phase handshake.
I think they should just be "req/ack", regardless if they are used synchronously (as "ready" signals).

Naming:

  • A_wren becomes A_out_req, and paired with a A_out_ack input.
  • A_rden becomes A_in_req, and paired with a A_in_ack input.

This change should be doable with a careful search/replace. Though please do it on a separate branch.