Kithmin Randula (kithminrw)

kithminrw

Geek Repo

Company:University of British Columbia

Location:Vancouver, Canada

Home Page:www.kithminrw.com

Twitter:@k1thR95

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Kithmin Randula's starred repositories

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

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amaranth

A modern hardware definition language and toolchain based on Python

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piel

Photonic Integrated ELectronics. Microservices to codesign photonics, electronics, quantum, and more.

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gdsfactory-generic-pdk

Generic Process Design Kit for Gdsfactory

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kfactory

gdsfactory with a klayout backend

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gplugins

gdsfactory plugins

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gdsfactory

python library to design chips (Photonics, Analog, Quantum, MEMs, ...), objects for 3D printing or PCBs.

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SciMLTutorials.jl

Tutorials for doing scientific machine learning (SciML) and high-performance differential equation solving with open source software.

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deep-learning

A deep-dive on the entire history of deep-learning

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8-bit-CPU

Verilog code for 8 bit CPU architecture design and testbench.

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Eko_study

Functions used for the study

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vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

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icc2_workshop_collaterals

This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efabless Corp. Pvt. Ltd. VSD has not checked functionality for these collaterals, so please do not expect a functionality bug fix. These are used purely for PNR workshops and trainings

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lilianweng.github.io

My personal page

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ecg-recon

ECG reconstruction

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biopython

Official git repository for Biopython (originally converted from CVS)

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bioinformatics-compbio-tools

A curated list of useful bioinformatics and computational biology tools, sorted by category.

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build-nanogpt

Video+code lecture on building nanoGPT from scratch

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PyTorch-GAN

PyTorch implementations of Generative Adversarial Networks.

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tinytapeout-08

Tiny Tapeout 8

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cgra4ml

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

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al-folio

A beautiful, simple, clean, and responsive Jekyll theme for academics

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firesim

FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility

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biosignalGANs

Adversarial learning models for biological signals including artificial synthesis and modality transfer.

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skywater-pdk-sky130-raw-data

Raw data collected about the SKY130 process technology.

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Ngspice-on-Colab

Sandbox for experimenting with Ngspice and open PDKs in Google Colab

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awesome_photonics

😎 curated list of open source photonics projects

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serdespy

Python library for SerDes modelling

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sky130_od_ip__tempsensor

Temperature sensor design in sky130 technology by Or Dicker (Chipalooza challenge 2024)

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