jzfengziyan / shufflenetv2_hls

A FPGA-based Accelerator for Shufflenetv2 implemented on Xillinx Zynq-7000 SoC

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A FPGA-based Accelerator for Shufflenetv2 implemented on Xillinx Zynq-7000 SoC


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Language:Ada 47.4%Language:VHDL 17.1%Language:C++ 13.0%Language:Verilog 11.8%Language:LLVM 8.7%Language:HTML 0.9%Language:Tcl 0.7%Language:C 0.2%Language:SystemVerilog 0.1%Language:Stata 0.0%Language:Scala 0.0%Language:Makefile 0.0%Language:Shell 0.0%Language:JavaScript 0.0%Language:Jupyter Notebook 0.0%Language:Assembly 0.0%Language:Python 0.0%Language:Forth 0.0%Language:Batchfile 0.0%Language:CartoCSS 0.0%Language:Pascal 0.0%Language:Ruby 0.0%Language:Coq 0.0%Language:1C Enterprise 0.0%