A RISC-V interpreter written in Rust.
This project is in early stages and it primarily being embarked upon as a learning exercise. Feel free to contribute and get involved if you would like to learn more about assembly and RISC-V.
- [ ] Implement RV32I:
- LUI
- AUIPC
- ADDI
- SLTI
- SLTUI
- XORI
- ORI
- ANDI
- SLLI
- SRLI
- SRAI
- ADD
- SUB
- SLL
- SLT
- SLTU
- XOR
- SRL
- SRA
- OR
- AND
- FENCE
- FENCE.I
- CSRRW
- CSRRS
- CSRRC
- CSRRWI
- CSRRSI
- CSRRCI
- ECALL
- EBREAK
- LB
- LH
- LW
- LBU
- LHU
- SB
- SH
- SW
- JAL
- JALR
- BEQ
- BNE
- BLT
- BGE
- BLTU
- BGEU
- [ ] Implement privileged RV32I:
- URET
- SRET
- MRET
- WFI
- SFENCE.VMA
- Implement basic model of the processor, instructions, stack and heap (based on a useful subset of all the instructions)
- Implement a parser for RISC-V assembly files
- Interpret and run RISC-V assembly files
- A graphical UI for inspecting the current processor state during the execution of a programme
- An assembler to create native RISK-V binaries
We follow the Rust code of conduct.
The moderation team consists of:
- John Bell (@johnabell)
- Andy Balaam (@andybalaam)
We welcome more members: if you would like to join the moderation team, please contact John Bell.
The project is licensed under the# GNU Affero General Public License v3.0.