jadephilipoom / oak-hardware

Formal specification and verification of hardware, especially for security and privacy.

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Project Oak Hardware Development

This repository contains code for circuits and verification related to Project Oak.

One of the experiments in this repo is an attempt to use the Kami system to define a simple counter circuit and drive the implementation process all the way from Kami/Coq via Bluespec to Verilog and then using the Vivado Xilinx FPGA tools to produce a running demo on the Xilinx ZCU104 development board.

We will soon add an example thow shows a totally open source flow for mapping to Lattice FPGAs.

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Formal specification and verification of hardware, especially for security and privacy.

License:Apache License 2.0


Languages

Language:Coq 78.2%Language:Haskell 8.1%Language:Makefile 5.3%Language:SystemVerilog 3.1%Language:Tcl 1.5%Language:VHDL 1.4%Language:Nix 1.2%Language:C++ 0.5%Language:Stata 0.3%Language:OCaml 0.2%Language:Shell 0.2%Language:Verilog 0.1%