jackiexiuyi's repositories
Cores-SweRV
SweRV EH1 core
Apache-2.0000
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
Language:Verilog000
amiga2000-gfxcard
MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog
Language:Verilog000
e200_opensource
The Ultra-Low Power RISC Core
Language:VerilogApache-2.0000
spi-slave
SPI Slave for FPGA in Verilog and VHDL
Language:VerilogMIT000
HDMI-to-FPGA-to-APA102-Pixels
Final Project written in Lucid (verilog) for the Mojo FPGA development board. Reads pixels from HDMI and sends pixel data to 22,000 APA102 LEDs over SPI.
Language:Verilog000
hw
RTL, Cmodel, and testbench for NVDLA
Language:VerilogNOASSERTION000
riscvv
an open source uvm verification platform for e200 (riscv)
Language:VerilogGPL-3.0000
Language:SystemVerilogNOASSERTION000
SPI_SLAVE_Verilog
SPI_SLAVE using verilog
Language:Verilog000
vSPI
Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah USB/SPI adapter
Language:XSLT000