Beast code in Giters

j054n's starred repositories

firmware-nordic-thingy91

Edge Impulse firmware for Nordic Thingy91

Language:CApache-2.01200

AWS-F1-Developer-Labs

AWS F1 Xilinx Developer Labs

Language:C++2800

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

Language:C++BSD-3-Clause252900

pp4fpgas

Parallel Programming for FPGAs -- An open-source high-level synthesis book

Language:TeXCC-BY-4.078300

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.

Language:VerilogApache-2.046100

blockchain-demo

A web-based demonstration of blockchain concepts.

Language:PugMIT520400

CNC_ControlPanel

CNC Control Panel project built for Element 14 Presents.

Language:C++400

GRBL_STM32

An open source, embedded, high performance g-code-parser and CNC milling controller written in optimized C that will run on a straight STM32F7X

Language:C2800

grbl-stm32

An open source, embedded, high performance g-code-parser and CNC milling controller. This is a port of GRBL 1.1 to STM32F10X target.

Language:CGPL-3.07300

grbl

An open source, embedded, high performance g-code-parser and CNC milling controller written in optimized C that will run on a straight Arduino

Language:CNOASSERTION556100

VSCode-Maxim

VSCode project folders for the Analog Devices MSDK

Language:MakefileNOASSERTION2300

ZYBO

Language:C6100

hdmi

Send video/audio over HDMI on an FPGA

Language:SystemVerilogNOASSERTION108000

x-cube-azrtos-h7

X-CUBE-AZRTOS-H7 (Azure RTOS Software Expansion for STM32Cube) provides a full integration of Microsoft Azure RTOS in the STM32Cube environment for the STM32H7 series of microcontrollers.

Language:CNOASSERTION14900

Digital

A digital logic designer and circuit simulator.

Language:JavaGPL-3.0431300

HLS-Tiny-Tutorials

This is forked from Xilinx HLS-Tiny-Tutorial. I'm learning HLS and adding Verilator testbench to verify the generated RTL

NOASSERTION2300

Vitis-Tutorials

Vitis In-Depth Tutorials

Language:CMIT120800

Pathsy

Simple Path Tracer on an FPGA

Language:SystemVerilogApache-2.03400

vivado-library

Language:CMIT56300

Probable-Wordlists

Version 2 is live! Wordlists sorted by probability originally created for password generation and testing - make sure your passwords aren't popular!

CC-BY-SA-4.0865000

airgeddon

This is a multi-use bash script for Linux systems to audit wireless networks.

Language:ShellGPL-3.0641100

verga

Verga is the Verilog simulator, written by Jeffery P. Hansen for the TkGate digital circuit editor and simulator. This project (Verga++) is the standalone version of Verga ported to C++ language.

Language:C++GPL-2.0100