ivanvig

Ivan's repositories

2dconv-FPGA

A 2D convolution hardware implementation written in Verilog

Language:VerilogMIT39 4 1

MIPS

32-bit MIPS Implementation in Verilog

Language:VerilogMIT300

ElectronicaDigital3-UNC

Repositorio para trabajar sobre los codigos de Electronica Digital III

Language:C1 10

paralela-unc-2018

Language:C1 10

svunit

Language:SystemVerilogApache-2.0102

API-REST-FcefynApp

RESTful API using Flask for the FcefynApp project

Language:Python010

AppLayer

Trabajo Practico n 7 - Redes de Computadoras - FCEFyN UNC

Language:Shell030

chisel-1st-try

Language:ScalaUnlicense010

chisel3

Chisel 3: A Modern Hardware Design Language

Language:ScalaApache-2.0000

FCN-car-segmentation

A Fully Convolutional Network for car sergmentation

Language:Python020

dotfiles

My personal configuration files for different applications

Language:Vim script010

ivanvig.github.io

Language:HTML010

jupiter

chess engine developed in C

Language:C010

kitty-themes

A collection of themes for kitty terminal 😻

Language:PythonMIT000

pyverilator

Python wrapper for verilator model

Language:PythonMIT003

pyxsi

Python/C/RTL cosimulation with Xilinx's xsim simulator

Language:C++NOASSERTION003

redox

Mirror of https://gitlab.redox-os.org/redox-os/redox

Language:MakefileMIT000

symbolator

Generate symbols from HDL components/modules

Language:PythonMIT000

system-install

Personal repository to speed up my ArchLinux system installation

010

unc-concurrente-2017

Language:Java020

unc-so2-2019

Language:TeX010