Incorrect values being reported for Zen+ Picasso processor
bimmerdriver opened this issue · comments
I'm using ZenTimings 1.2.1 to look at timings for a Ryzen 5 3400G using Gigabyte B450 Aorus M motherboard. ZT is reporting wildly fluctuating FCLK (~1500 to 9000) and it's reporting VSOC, which should be Vcore. Let me know if you need more information, such a debug log.
I have a 3000G and can test it. Newest I have is a 370X board, though.
SVI lanes are probably switched on Picasso, compared to Raven Ridge.
The other issue you have is that the FCLK has s dynamic frequency depending on the load, but I don't know why it reports so high upper limit. I can switch to the other value, which will report the FCLK set value, instead of the dynamic one.
Already did for Renoir, because people were complaining about the variable FCLK.
FCLK is all over the place. At times goes well over 10000.
To me it seems a different table version. Would you run a debug with the latest build?
ZenTimings_v1.2.2.119_debug.zip
Here you go. FCLK still jumping around and VSOC still displaying Vcore.
Yes, there's no change in the way it reads them, but the newest build includes table version in the debug log.
Thanks, will get back to you when I have a test build.
Your table version is the same as mine, but you have way older SMU version. VSOC looks ok on mine, but I guess will need adjustment on your older SMU version bios. Could you check if HWinfo reads SoC Voltage (SVI2 TFN) correctly?
I could probably fix the rest relatively easy.
VSOC reported by ZenTimings is CPU Core Voltage (SV12 TFN) reported by HWiNFO v641-4335.
I'm running the most recent available BIOS.
Thanks.
Your bios has SMU version 30.75.00, while mine is running 37.48.00.
Apparently SVI2 addresses changed somewhere between those 2 versions, but without the changelog and documentation I can't know when. In your version the addresses are switched (or from another point of view, they are switched on mine).
HWinfo knows about it, it seems. I can make a fix, but it won't be perfect and will potentially lead to more inconsistency if someone has a bios with different SMU version than these two.
I get why The Stilt abandoned his project long time ago, it's impossible to keep up with all the changes.
PS: Your bios uses the addresses for Zen/Zen+, while mine uses Zen2 addresses.
Can you, please, check what's the SMU version HWInfo reports?
I have a feeling you might have 4.30.75.00 version instead.
PS: I have a test build ready
ZenTimings_v1.2.2.119_debug2.zip
Here is the line from HWiNFO: SMU Firmware Revision: 4.30.75.0
Is this out of date? If so, should I open a ticket with Gigabyte or AMD and ask if there will be an update?
Thank you for your support.
Ok, as suspected. It's recent enough, I think.
Maybe they are using different firmware, because mine is labeled as Athlon and yours is Ryzen.
Perhaps something to do with the integrated Vega GPU, although both are detected as Picasso.
Might depend on the vendor as well, don't really know.
Thanks for the reports, you helped a ton!
There's a high chance this build works fine now.
ZenTimings_v1.2.2.120.zip
Thank you very much for the fix.
FCLK is stable now. On my system, MCLK, FCLK and UCLK are the same, 1600.
Also, VSOC is stable now at 1.1V, which is the same as HWiNFO. FYI, HWiNFO has two values, a stable value that it reports as SoC Voltave (SV12 TFN), the same as ZenTimings is reporting, as well as a dynamic value that it reports as CPU VCORE SOC.
If you ever need anyone with a 3400G to test, don't hesitate to let me know.
This specific case should be fixed in v1.2.2, although there might be more cases which are not covered.