intel / fpga-npu

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Issue with compiling RTL design in Aldec Riviera-PRO

dominiksapeta opened this issue · comments

It seems like in files rtl/mvu.sv, rtl/mvu_tile.sv, rtl/npu.sv and rtl/shim.sv parameters are used before declaration. The error is pointing to the parameter MRFIDW, which uses an undeclared identifier NUM_DSP. Macros used for initialization are from rtl/npu.vh.

Moving declarations of PRIME_DOTW and NUM_DSP above MRFIDW seems to fix the issue.