tRTP and tWR are linked
junkmannn opened this issue · comments
I'm surprised no one seems to mention this anywhere, but these timings mutually drive each other. The rule is tWR = 2*tRTP. These two are configured via the Mode Register 0 (MR0) in the memory.
Taken from the Micron Rev E datasheet but it's the same for all DDR4 afaik.
tWR and tRTP does not provide much of performance uplift so we could have ignored them and left them to the end, but!! lower tRTP could mean lower tRAS and here where is the performance uplift comes from that's why these timings really matters especially for micron rev E ones. Micron can do very low tRP, tRAS, tRTP, tWTRS and tWTRL compared to other types of memory chips so spending some time on lowering tWR totally worth it rather than leaving it to the end. The order should be like this:
tRP >> tWR >> tRTP >> tRAS >> tRC.
I Think the best results would be achieved with this order.
Addressed in 13fa314