tRP, tRTP and tRAS

[IslamGhunym]

I wanted to share my findings here so it can hopefully be useful.
The memory OC I was doing was on ASUS B450M-A with 3400G APU and 2 x 8 GB DDR4 micron Rev E single rank dual channel.
Anyway, I read the guide countless times really and spent months messing with timings and frequencies. The maximum achieveable with my samples was 3466. I was not able to stabilise the 3533.. tried everything really including resistance. However the graphic unit was crashing bellow 1.25v SOC at 3466. each a frequency step I went over 2933 required a higher SOC voltage in order not to crash on 3D applications. I have seen no negative scaling with higher SOC voltage up to 1.35v which is something nice. However over 1.45v DRAM voltage I started to see no better results because I was clearly limited by the picasso IMC in everything. a 3533 however will require higher than 1.25v SOC which will put me into unsafe voltage range considering PBO was enabled and may push SOC voltage as high as 1.32V in some rare cases. So 3466 was my limit here.
I was able to run 14 tCL and no lower than that at 3333, 3400 and 3466. The same story goes for tRCD and tRP and other timings as well was not effected by higher frequency on 1.45v except tRC and tRFC

Anyway, what I wanted to add is this:

I was able to run tRP as low as 11 and it scales with voltage even tho in your guide for Rev E chips, it is written that it does not scale with higher voltage, but when I followed the order in your guide about timings tRP was not stable bellow 18 = tRCD which looks like it does not scale with voltage just like tRCD. I tried a different order of tightening timings (the same order I did previously) than the order in your guide and I was able to go as low as 11 for tRP. tRCD however was the same can't be lower than 18.

So why I had different findings?
The thing is tRP, tRAS, tRTP, tWR and tRC have relations.
Running lower tWR made lower tRTP stable.
Tightening tRTP and tWR before tRP made tRP unable to run bellow 18 and benchmarks showed a clear drop in the read and write bandwidth and 2 more ns latency, but when I tightened tRP first I could go as low as 11, but that required higher tRTP, but there was a real performance difference. Well tRP is a major timing of course so having it lower shall do better.

So what I wanted to say maybe the order this way would give better results:
tRP >> tWR >> tRTP >> tRAS >> tRC.
Of course I am not better than any of you to explain why, but this is what my experiment have shown so hopefully it can be useful.