I believe the tRAS equation in the guide, isnt quite correct.

[GenTarkin]

Hi,
So, I have pondered on your suggestion of the equation you propose to determine tRAS being:
tRCD + tRTP = tRAS

And while I believe thats correct in the manner you stated "tRTP" ... but the problem is on that graphic from the anandtech article that you reference ... tRTP isnt shown on it, furthermor .. the tRTP setting in my bios anyways is more akin to the Fig 7 graphic from: https://www.anandtech.com/show/3851/everything-you-always-wanted-to-know-about-sdram-memory-but-were-afraid-to-ask/5
and not necessarily the definition you provide when referring to the graphic you posted (because such timing is missing from it).

So, after reading anandtech's article and looking at some of the RAM operation types and their graphics (the page hit, page miss and page empty) graphics ... and when looking at the graphic you posted.
Ive come up with following equation that seems to ,at least be more in "spirit", of the timings shown between all those graphics.
So, using the graphic you provided, I believe this is how you would calculate the "tRTP" you reference:
"tRTP" = CL + tBurst(4 on DDR3/4 afaik) + 2
therefore
tRAS = tRCD + CL + tBurst(4T on DDR3/4 afaik) + 2

While this might sound high .. when reading through the anandtech article .. it seems that using this equation .. allows all the operations except tRP fit nicely into the tRAS window + 2 clock "padding" (idk if the +2 is necessary, it may not be and may without the +2 that could be considered "minimum tRAS") ..when I reference the stock timings on my RAM, the +2 is not part of tRAS(but for some reason the pic you reference has those extra 2 clocks(maybe a DDR3 vs DDR4 variance? idk)).

Now one possible variance I can see, is I think anandtechs article is about DDR3 ... perhaps the requirements/ window / timing for tRAS has been modified in DDR4? idk.

My initial testing results with my memory testing / tweaking considering the above...
Ive been testing my DDR4 @ 3800 - 17 - 19 - 19 - 38 (based on your current equation) ... and seems to work fine.
Ive changed the 38 to 42 ... based on my new equation, and so far I havent seen any noticeable performance loss in aida64 at least. In fact, upping it to 42 alone allowed me to increase IOL offsets another 2 notches, brining my latency down even more.

Anywho, perhaps something worth exploring =)

[integralfx]

"tRTP" = CL + tBurst(4 on DDR3/4 afaik) + 2

You should be looking at the command section rather than calculating the clock cycles. It just so happens that

• tCL = 6
• tRCD = 6
• tRTP = 12
• tRAS = 18

so you can say that tRAS = tCL + tRTP which holds true for the above timings but that doesn't mean it will be true overall. It just so happens that tCL and tRCD are both 6 which may mislead people into thinking that.

Likewise with your suggested formula. It just so happens that tBurst + 2 == tRCD which is probably how you thought up that formula.

As explained in my guide and also referenced here

The minimum time between a row of memory being activated and precharged.

Therefore, tRAS is the time between ACT and PRE commands.

Hope this clears things up for you. :)

[Arshia]

That formula is physically not possible. tBURST does not begin until to precharge is completed. Precharging period ends the second the cell read begins, so that charge is maintained on the line. if tBURST was a portion of the RAS period, the line would not be precharged as the read operation took place, which means the dual sense amplifiers literally could not compare negatively to positive relative voltages on the precharged lines.

If you need precharging to read, precharging cannot be part of the period before precharge commands begin. that +2 is a misinterpretation of the graph. that graph depicts a RCD of 2nCK, with tBURST always taking up 2nCK. this is a commonly misinterpreted image, like even Raja from Asus cant seem to comprehend it, and that isn't without reason. Simply put, this is why I stick to JEDEC graphs, which clearly outline the specific timing parameters and choose numbers that leave little up in the air. tCL is simply just going to open the first column in the burst, hence why its called tAA in JEDEC (Internal read command to first data), as its literally only the first bit in the burst. This 4nCK of tBurst is always present. anyways that +2 is a misinterpretation, as is the formula. Its a case of specific timings and unclear/unlaballed graphs.\

tRCDRD + tRTP for read operations and tWR + tBC (4) + tRCDWR + tCWL is the minimum scaling tRAS period, with lower values possible but with 0 impact

PS: oftentimes AL is what actually matters, so you would probably see near-identical stability from lower tRAS and tRTP by 2 each respectively on your tRAS 42 setup, since this would maintain the same AL of 4 whilst lowering tRCD and RAS command period. should allow same change to IOL as before.