FEC
FEC Codec IP core library for some famous codes (BCH, RS, LDPC, Turbo, Polar and etc)
FEC IP cores are synthesable and self-documented RTL code (System Verilog) with limited functionality and performance to explore or using for any applications.
The library contain:
- BCH code with optional erasures
- RS code with optional erasures
- Viterby code for soft-decoding
- DVB/Wimax RSC duo-binary turbo code
- NASA GSFC LDPC code
- Wimax LDPC code
- 3GPP LDPC code
- 3GPP Polar code
- Soft decision Golay code
- DVB-S2/S2X LDPC code
- CCSDS Turbo code
- 4D-8PSK TCM code
- Hamming code
- QAM LLR demappers
- DVB-S2 PLS code
All FEC IP Cores has static configuration and constrained performance. Call me if you need any IP core extension