ikwzm / SECURE_HASH

SHA-1,SHA-256,SHA-512 Secure Hash Generator written in VHDL(RTL) for FPGA(Xilinx and Altera).

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Simplify SHA256

Hardcore-fs opened this issue · comments

maybe :

function Maj(B,C,D:WORD_TYPE) return std_logic_vector is
begin
return (B and C) or (B and D) or (C and D);
end function;

can become:

return (x and y) or (z and (x or y))

which is one less logical operator over a 32 bit product

and

function Ch(B,C,D:WORD_TYPE) return std_logic_vector is
begin
return (B and C) or ((not B) and D);

can be:

z xor (x and (y xor z))

These simplifications are clearly documented in

Thank you.