Integrated Circuits Lab @ DUTH (ic-lab-duth)

ic-lab-duth

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Location:Xanthi, Greece

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Integrated Circuits Lab @ DUTH's repositories

RISC-V-Vector

Vector processor for RISC-V vector ISA

Language:SystemVerilogLicense:NOASSERTIONStargazers:103Issues:7Issues:0

DRIM-S

DUTH RISC-V Superscalar Microprocessor

Language:SystemVerilogLicense:MITStargazers:28Issues:3Issues:0

NoCpad

HLS for Networks-on-Chip

Language:C++License:NOASSERTIONStargazers:27Issues:6Issues:0

FusedGCN4HLS

Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis

Language:C++License:MITStargazers:20Issues:2Issues:1

DRIM

DUTH RISC-V Microprocessor

Language:SystemVerilogLicense:MITStargazers:18Issues:3Issues:0

Fast-Float4HLS

Fast Floating Point Operators for High Level Synthesis

Language:C++License:MITStargazers:16Issues:3Issues:0

DRIM4HLS

DUTH RISC V Microprocessor for High Level Synthesis

Language:C++License:Apache-2.0Stargazers:9Issues:2Issues:0

shared-buffer-hw

A multi-queue buffer with dynamic buffer space allocation and its Formal Verification TB

Language:SystemVerilogLicense:NOASSERTIONStargazers:2Issues:1Issues:0

Data-Clustering-HLS-Lib

A C++ library of data clustering algorithms for High-Level Synthesis

Language:C++License:MITStargazers:1Issues:2Issues:0
Language:C++License:MITStargazers:1Issues:2Issues:0

ApproximatePrefix

Synthesis of Approximate Parallel Prefix Adders

Language:C++License:MITStargazers:0Issues:2Issues:0

CompArchCourseDUTH

Material related to the Computer Architecture course at ECE, DUTH

Language:SystemVerilogStargazers:0Issues:1Issues:0
Language:C++License:MITStargazers:0Issues:0Issues:0