HITECHNOTACH

docs

TensorFlow documentation

EloquentArduino

IO, scheduling, utils, machine learning... for Arduino

gatery

Gatery, a library for circuit design.

gatery_template

mqttlog

A logging backend for "github.com/op/go-logging" to send messages to one or more MQTT topics

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

PLC_Programming

Rockwell Automation RSLogix 500 Programs

qiskit

Qiskit is an open-source framework for working with noisy quantum computers at the level of pulses, circuits, and algorithms.

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

riscv-trace-spec

Working Draft of the RISC-V Processor Trace Specification

Vitis-HLS-Introductory-Examples

foundation

Governance-related CHIPS Alliance documents, guides etc.

gap_sdk

SDK for Greenwaves Technologies' GAP8 IoT Application Processor

HLS

Vitis HLS LLVM source code and examples

linux

Linux kernel source tree

nodeS7

Node.JS library for communication to Siemens S7 PLCs

OpenFPGA

An Open-source FPGA IP Generator

openfpga-1

Open FPGA tools

openFPGALoader

Universal utility for programming FPGA

OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

p4c

P4_16 prototype compiler

risc-v-core

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research