hachembensalem's repositories
ava-core
A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Cores-SweRV
SweRV EH1 core
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
dromajo
RISC-V RV64GC emulator designed for RTL co-simulation
FABulous
Fabric generator and CAD tools
fwrisc
Featherweight RISC-V implementation
iob-soc
RISC-V System on Chip Template Based on the picorv32 Processor
kianRiscV
kianv a simple implementation of a rv32im riscv cpu and soc in verilog with firmware that runs raytracer, mandelbrot, etc.....
Learn-FPGA-Programming
Learn FPGA Programming, published by Packt
meta-riscv
OpenEmbedded/Yocto layer for RISC-V Architecture
microwatt-caravel
Integrate Microwatt into Caravel. Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
potato
A simple RISC-V processor for use in FPGA designs.
pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
rars
RARS -- RISC-V Assembler and Runtime Simulator
Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
riscv-crypto
RISC-V cryptography extensions standardisation work.
riscv-platform-specs
RISC-V Profiles and Platform Specification
rsd
RSD: RISC-V Out-of-Order Superscalar Processor
rvalp
RISC-V Assemly Language Programming
SweRV-Support-Package-free
Design environment for SoC and software design using SweRV EH1 core
Toooba
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
vroom
VRoom! RISC-V CPU
XiangShan
Open-source high-performance RISC-V processor
yosys
Yosys Open SYnthesis Suite
zipcpu
A small, light weight, RISC CPU soft core