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XLS: Accelerated HW Synthesis

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FIFO Metadata Specification

grebe opened this issue · comments

Currently, the FifoConfig construct has fields for fifo depth and bypass. Bypass, which is not carefully specified, may imply combinational coupling between push- and pop-side signals. The combinational coupling between signals should be specified in greater detail.

The only mechanism we have in DSLX to specify FIFO metadata is an undocumented feature where you optional include the fifo depth in the channel declaration, e.g. chan<some_type, fifo_depth>(...). This feature should be documented and perhaps changed to something better.

We need a way to specify other fifo metadata, like bypass or more detailed combinational coupling and latency behavior. Most of this metadata does not effect the semantics at proc-level evaluation, so perhaps it should be bound via configuration at codegen. Now that internal channels are getting better names, perhaps binding fifo configuration by name is the way to go.

This fifo metadata should factor into scheduling and codegen. Scheduling needs to be aware of combinational coupling (e.g. a recv's in one stage may be ready after as the send in its stage depending on fifo metadata. Similarly, combo loops may occur unless care is taken in block conversion (e.g. pop_ready may imply push_ready in the same cycle and allow you to remove some logic (which may also avoid combo loops)).