Support temporal logic assertions

[Ted Hong]

So that designers can utilize assertions akin to the assertions they are used to in SV, DSLX/XLS should support somthing akin to SV's LTL assertions.

Note that one complication is that unlike verilog, an XLS proc does not have an exact notion of a clock or about the latency/sequence of operations.

[Chris Leary]

Note that @allight implemented a first step towards bounded model checking (i.e. unrolling proc iterations to check properties across time steps) in bfd2e39