got an issue in digilent_arty.fasm when building bitstream
ggangliu opened this issue · comments
Hi
I ran into below issue when executing "make bitsteram USE_SYMBIFLOW=1". But I guess it is very close to the final success, thanks for your help in advance.
ggang@ubuntu:~/CFU-Playground/proj/proj_template$ make bitstream USE_SYMBIFLOW=1
make[4]: Entering directory '/home/ggang/CFU-Playground/proj/proj_template'
/home/ggang/CFU-Playground/scripts/pyrun /home/ggang/CFU-Playground/proj/proj_template/cfu_gen.py
make -C /home/ggang/CFU-Playground/soc -f /home/ggang/CFU-Playground/soc/common_soc.mk bitstream
make[5]: Entering directory '/home/ggang/CFU-Playground/soc'
Building bitstream for digilent_arty. CFU option: --cpu-cfu /home/ggang/CFU-Playground/proj/proj_template/cfu.v
MAKEFLAGS=-j8 /home/ggang/CFU-Playground/scripts/pyrun ./common_soc.py --output-dir build/digilent_arty.proj_template --csr-json build/digilent_arty.proj_template/csr.json --cpu-cfu /home/ggang/CFU-Playground/proj/proj_template/cfu.v --uart-baudrate 1843200 --target digilent_arty --toolchain symbiflow --build
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2022-01-15 19:02:41)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc7a35ticsg324-1L.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU overriding rom mapping from 0x0 to 0x0.
INFO:SoC:CPU overriding sram mapping from 0x1000000 to 0x10000000.
INFO:SoC:CPU overriding main_ram mapping from 0x40000000 to 0x40000000.
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:S7PLL:Creating S7PLL, speedgrade -1.
INFO:S7PLL:Registering Single Ended ClkIn of 100.00MHz.
INFO:S7PLL:Creating ClkOut0 sys of 100.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut1 sys4x of 400.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut2 sys4x_dqs of 400.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut3 idelay of 200.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut4 eth of 25.00MHz (+-10000.00ppm).
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:S7PLL:Config:
divclk_divide : 1
clkout0_freq : 100.00MHz
clkout0_divide: 16
clkout0_phase : 0.00°
clkout1_freq : 400.00MHz
clkout1_divide: 4
clkout1_phase : 0.00°
clkout2_freq : 400.00MHz
clkout2_divide: 4
clkout2_phase : 90.00°
clkout3_freq : 200.00MHz
clkout3_divide: 8
clkout3_phase : 0.00°
clkout4_freq : 25.00MHz
clkout4_divide: 64
clkout4_phase : 0.00°
vco : 1600.00MHz
clkfbout_mult : 16
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 4).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:ddrphy CSR allocated at Location 1.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 2.
INFO:SoCCSRHandler:leds CSR allocated at Location 3.
INFO:SoCCSRHandler:sdram CSR allocated at Location 4.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 5.
INFO:SoCCSRHandler:uart CSR allocated at Location 6.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (4)
rom : Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False
sram : Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
main_ram : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (4)
- rom
- sram
- main_ram
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (7)
- ctrl : 0
- ddrphy : 1
- identifier_mem : 2
- leds : 3
- sdram : 4
- timer0 : 5
- uart : 6
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart : 0
- timer0 : 1
INFO:SoC:--------------------------------------------------------------------------------
make[6]: Entering directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/libc'
if [ -d "/home/ggang/CFU-Playground/third_party/python/litex/litex/soc/software/libc/riscv" ]; then \
cp /home/ggang/CFU-Playground/third_party/python/litex/litex/soc/software/libc/riscv/* /home/ggang/CFU-Playground/third_party/python/pythondata-software-picolibc/pythondata_software_picolibc/data/newlib/libc/machine/riscv/ ;\
fi
meson /home/ggang/CFU-Playground/third_party/python/pythondata-software-picolibc/pythondata_software_picolibc/data \
-Dmultilib=false \
-Dpicocrt=false \
-Datomic-ungetc=false \
-Dthread-local-storage=false \
-Dio-long-long=true \
-Dformat-default=integer \
-Dincludedir=picolibc/riscv64-unknown-elf/include \
-Dlibdir=picolibc/riscv64-unknown-elf/lib \
--cross-file cross.txt
WARNING: Unknown CPU family riscv, please report this at https://github.com/mesonbuild/meson/issues/new
The Meson build system
Version: 0.60.99
Source dir: /home/ggang/CFU-Playground/third_party/python/pythondata-software-picolibc/pythondata_software_picolibc/data
Build dir: /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/libc
Build type: cross build
Project name: picolibc
Project version: 1.7.2
C compiler for the host machine: riscv64-unknown-elf-gcc (gcc 10.1.0 "riscv64-unknown-elf-gcc (SiFive GCC 10.1.0-2020.08.2) 10.1.0")
C linker for the host machine: riscv64-unknown-elf-gcc ld.bfd 2.35.0-2020
C compiler for the build machine: ccache cc (gcc 9.3.0 "cc (Ubuntu 9.3.0-17ubuntu1~20.04) 9.3.0")
C linker for the build machine: cc ld.bfd 2.34
Build machine cpu family: x86_64
Build machine cpu: x86_64
Host machine cpu family: riscv
Host machine cpu: vexriscv
Target machine cpu family: riscv
Target machine cpu: vexriscv
Compiler for C supports arguments -fno-stack-protector: YES
Compiler for C supports arguments -fno-common: YES
Compiler for C supports arguments -frounding-math: YES
Program riscv64-unknown-elf-gcc-nm found: YES
Program scripts/duplicate-names found: YES (/home/ggang/CFU-Playground/third_party/python/pythondata-software-picolibc/pythondata_software_picolibc/data/scripts/duplicate-names)
Compiler for C supports link arguments -Wl,--defsym=_start=0: YES
Compiler for C supports link arguments -Wl,-alias,main,testalias: NO
Compiler for C supports function attribute alias: YES
Compiler for C supports function attribute format: YES
WARNING: You should add the boolean check kwarg to the run_command call.
It currently defaults to false,
but it will default to true in future releases of meson.
See also: https://github.com/mesonbuild/meson/issues/9300
Configuring picolibc.specs using configuration
Configuring picolibcpp.specs using configuration
Configuring test.specs using configuration
Configuring picolibc.ld using configuration
Configuring picolibcpp.ld using configuration
Compiler for C supports arguments -Wno-missing-braces: YES
Compiler for C supports arguments -Wno-implicit-int: YES
Compiler for C supports arguments -Wno-return-type: YES
Compiler for C supports arguments -Werror=implicit-function-declaration: YES
Compiler for C supports arguments -Werror=vla: YES
Checking if "long double check" : compiles: YES
Checking if "long double same as double" : compiles: NO
Checking if "packed structs may contain bitfields" : compiles: YES
Checking if "has __builtin_mul_overflow" : links: YES
Checking if "supports _Complex" : compiles: YES
Checking if "has __builtin_expect" : links: YES
Compiler for C supports arguments -Werror: YES
Checking if "attribute __alloc_size__" : compiles: NO
Compiler for C supports arguments -Werror: YES (cached)
Checking if "attributes constructor/destructor" : compiles: YES
Checking if "test for __builtin_alloca" : links: YES
Checking if "test for __builtin_ffs" : links: YES
Checking if "test for __builtin_ffsl" : links: YES
Checking if "test for __builtin_ffsll" : links: YES
Checking if "test for __builtin_ctz" : links: YES
Checking if "test for __builtin_ctzl" : links: YES
Checking if "test for __builtin_ctzll" : links: YES
Checking if "test for __builtin_copysignl" : links: NO
Checking if "test for __builtin_copysign" : links: NO
Checking if "test for __builtin_isinfl" : links: YES
Checking if "test for __builtin_isinf" : links: YES
Checking if "test for __builtin_isnanl" : links: YES
Checking if "test for __builtin_isnan" : links: YES
Checking if "test for __builtin_finitel" : links: YES
Checking if "test for __builtin_isfinite" : links: YES
Compiler for C supports arguments -fno-tree-loop-distribute-patterns: YES
Compiler for C supports arguments -fno-builtin: YES
Compiler for C supports arguments -ffunction-sections: YES
Compiler for C supports arguments -ftls-model=local-exec: YES
Message: host_cpu_family riscv
Compiler for C supports arguments -fstack-protector-all: YES
Compiler for C supports arguments -fstack-protector-strong: YES
Compiler for C supports arguments -fno-builtin-malloc: YES
Compiler for C supports arguments -fno-builtin-free: YES
Message: libc/string/memcpy.c: machine overrides generic
Message: libc/string/memmove.S: machine overrides generic
Message: libc/string/memset.S: machine overrides generic
Message: libc/string/strcpy.c: machine overrides generic
Message: libc/string/strlen.c: machine overrides generic
Message: libc/string/strcmp.S: machine overrides generic
Message: libc/include/sys/fenv.h: machine overrides generic
Message: libc/include/machine/math.h: machine overrides generic
Compiler for C supports arguments -fno-builtin-exp2: YES
Message: Set c_args_exp2
Message: libm/math/ef_sqrt.c: machine overrides generic
Message: libm/math/e_sqrt.c: machine overrides generic
Message: libm/math/s_fabs.c: machine overrides generic
Message: libm/math/sf_fabs.c: machine overrides generic
Message: libm/common/s_finite.c: machine overrides generic
Message: libm/common/s_copysign.c: machine overrides generic
Message: libm/common/s_isinf.c: machine overrides generic
Message: libm/common/s_isnan.c: machine overrides generic
Message: libm/common/s_fma.c: machine overrides generic
Message: libm/common/s_fmax.c: machine overrides generic
Message: libm/common/s_fmin.c: machine overrides generic
Message: libm/common/s_fpclassify.c: machine overrides generic
Message: libm/common/s_lrint.c: machine overrides generic
Message: libm/common/s_llrint.c: machine overrides generic
Message: libm/common/s_lround.c: machine overrides generic
Message: libm/common/s_llround.c: machine overrides generic
Message: libm/common/sf_finite.c: machine overrides generic
Message: libm/common/sf_copysign.c: machine overrides generic
Message: libm/common/sf_isinf.c: machine overrides generic
Message: libm/common/sf_isnan.c: machine overrides generic
Message: libm/common/sf_fma.c: machine overrides generic
Message: libm/common/sf_fmax.c: machine overrides generic
Message: libm/common/sf_fmin.c: machine overrides generic
Message: libm/common/sf_fpclassify.c: machine overrides generic
Message: libm/common/sf_lrint.c: machine overrides generic
Message: libm/common/sf_llrint.c: machine overrides generic
Message: libm/common/sf_lround.c: machine overrides generic
Message: libm/common/sf_llround.c: machine overrides generic
Message: libm/fenv/feclearexcept.c: machine overrides generic
Message: libm/fenv/fegetenv.c: machine overrides generic
Message: libm/fenv/fegetexceptflag.c: machine overrides generic
Message: libm/fenv/fegetround.c: machine overrides generic
Message: libm/fenv/feholdexcept.c: machine overrides generic
Message: libm/fenv/feraiseexcept.c: machine overrides generic
Message: libm/fenv/fesetenv.c: machine overrides generic
Message: libm/fenv/fesetexceptflag.c: machine overrides generic
Message: libm/fenv/fesetround.c: machine overrides generic
Message: libm/fenv/fetestexcept.c: machine overrides generic
Message: libm/fenv/feupdateenv.c: machine overrides generic
Configuring picolibc.h using configuration
Build targets in project: 35
NOTICE: Future-deprecated features used:
* 0.58.0: {'meson.get_cross_property'}
picolibc 1.7.2
User defined options
Cross files : cross.txt
includedir : picolibc/riscv64-unknown-elf/include
libdir : picolibc/riscv64-unknown-elf/lib
atomic-ungetc : false
format-default : integer
io-long-long : true
multilib : false
picocrt : false
thread-local-storage: false
Found ninja-1.10.2.git at /usr/bin/ninja
meson compile
[918/918] Generating newlib/libc_duplicates with a custom command
cp newlib/libc.a __libc.a
CC _libc.a
AR _libc.a
cp __libc.a _libc.a
CC libc.a
AR libc.a
cp _libc.a libc.a
make[6]: Leaving directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/libc'
make[6]: Entering directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/libcompiler_rt'
CC umodsi3.o
CC udivsi3.o
CC divsi3.o
CC modsi3.o
CC comparesf2.o
CC comparedf2.o
CC negsf2.o
CC negdf2.o
/home/ggang/CFU-Playground/third_party/python/pythondata_software_compiler_rt/pythondata_software_compiler_rt/data/lib/builtins/comparedf2.c:85:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
85 | FNALIAS(__cmpdf2, __ledf2);
| ^~~~~~~
/home/ggang/CFU-Playground/third_party/python/pythondata_software_compiler_rt/pythondata_software_compiler_rt/data/lib/builtins/comparesf2.c:85:1: warning: function declaration isn't a prototype [-Wstrict-prototypes]
85 | FNALIAS(__cmpsf2, __lesf2);
| ^~~~~~~
CC addsf3.o
CC subsf3.o
CC mulsf3.o
CC divsf3.o
CC lshrdi3.o
CC muldi3.o
CC divdi3.o
CC ashldi3.o
CC ashrdi3.o
CC udivmoddi4.o
CC floatsisf.o
CC floatunsisf.o
CC fixsfsi.o
CC fixdfdi.o
CC fixunssfsi.o
CC fixunsdfdi.o
CC adddf3.o
CC subdf3.o
CC muldf3.o
CC divdf3.o
CC floatsidf.o
CC floatunsidf.o
CC floatdidf.o
CC fixdfsi.o
CC fixunsdfsi.o
CC clzsi2.o
CC ctzsi2.o
CC udivdi3.o
CC umoddi3.o
CC moddi3.o
CC ucmpdi2.o
CC mulsi3.o
AR libcompiler_rt.a
make[6]: Leaving directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/libcompiler_rt'
make[6]: Entering directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/libbase'
CC crc16.o
CC crc32.o
CC console.o
CC system.o
CC progress.o
CC memtest.o
CC uart.o
CC spiflash.o
CC i2c.o
AR libbase.a
make[6]: Leaving directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/libbase'
make[6]: Entering directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/libfatfs'
CC ffunicode.o
CC ff.o
AR libfatfs.a
make[6]: Leaving directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/libfatfs'
make[6]: Entering directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/liblitespi'
CC spiflash.o
AR liblitespi.a
make[6]: Leaving directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/liblitespi'
make[6]: Entering directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/liblitedram'
CC sdram.o
CC bist.o
CC sdram_dbg.o
AR liblitedram.a
make[6]: Leaving directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/liblitedram'
make[6]: Entering directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/libliteeth'
CC udp.o
CC tftp.o
CC mdio.o
/home/ggang/CFU-Playground/third_party/python/litex/litex/soc/software/libliteeth/tftp.c: In function 'tftp_get':
/home/ggang/CFU-Playground/third_party/python/litex/litex/soc/software/libliteeth/tftp.c:125:19: warning: passing argument 1 of 'udp_set_callback' from incompatible pointer type [-Wincompatible-pointer-types]
125 | udp_set_callback(rx_callback);
| ^~~~~~~~~~~
| |
| void (*)(uint32_t, uint16_t, uint16_t, void *, unsigned int) {aka void (*)(long unsigned int, short unsigned int, short unsigned int, void *, unsigned int)}
In file included from /home/ggang/CFU-Playground/third_party/python/litex/litex/soc/software/libliteeth/tftp.c:15:
/home/ggang/CFU-Playground/third_party/python/litex/litex/soc/software/libliteeth/udp.h:19:36: note: expected 'udp_callback' {aka 'void (*)(unsigned int, short unsigned int, short unsigned int, void *, unsigned int)'} but argument is of type 'void (*)(uint32_t, uint16_t, uint16_t, void *, unsigned int)' {aka 'void (*)(long unsigned int, short unsigned int, short unsigned int, void *, unsigned int)'}
19 | void udp_set_callback(udp_callback callback);
| ~~~~~~~~~~~~~^~~~~~~~
/home/ggang/CFU-Playground/third_party/python/litex/litex/soc/software/libliteeth/tftp.c: In function 'tftp_put':
/home/ggang/CFU-Playground/third_party/python/litex/litex/soc/software/libliteeth/tftp.c:181:19: warning: passing argument 1 of 'udp_set_callback' from incompatible pointer type [-Wincompatible-pointer-types]
181 | udp_set_callback(rx_callback);
| ^~~~~~~~~~~
| |
| void (*)(uint32_t, uint16_t, uint16_t, void *, unsigned int) {aka void (*)(long unsigned int, short unsigned int, short unsigned int, void *, unsigned int)}
In file included from /home/ggang/CFU-Playground/third_party/python/litex/litex/soc/software/libliteeth/tftp.c:15:
/home/ggang/CFU-Playground/third_party/python/litex/litex/soc/software/libliteeth/udp.h:19:36: note: expected 'udp_callback' {aka 'void (*)(unsigned int, short unsigned int, short unsigned int, void *, unsigned int)'} but argument is of type 'void (*)(uint32_t, uint16_t, uint16_t, void *, unsigned int)' {aka 'void (*)(long unsigned int, short unsigned int, short unsigned int, void *, unsigned int)'}
19 | void udp_set_callback(udp_callback callback);
| ~~~~~~~~~~~~~^~~~~~~~
AR libliteeth.a
make[6]: Leaving directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/libliteeth'
make[6]: Entering directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/liblitesdcard'
CC sdcard.o
CC spisdcard.o
AR liblitesdcard.a
make[6]: Leaving directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/liblitesdcard'
make[6]: Entering directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/liblitesata'
CC sata.o
AR liblitesata.a
make[6]: Leaving directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/liblitesata'
make[6]: Entering directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/bios'
CC crt0.o
CC isr.o
CC boot-helper.o
CC boot.o
CC helpers.o
CC cmd_bios.o
CC cmd_boot.o
CC cmd_mem.o
CC cmd_i2c.o
CC cmd_spiflash.o
CC cmd_litedram.o
CC cmd_liteeth.o
CC cmd_litesdcard.o
CC cmd_litesata.o
CC sim_debug.o
CC main.o
CC complete.o
CC readline.o
CC bios.elf
chmod -x bios.elf
OBJCOPY bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/bios/../include/generated/regions.ld riscv64-unknown-elf
ROM usage: 24.69KiB (19.29%)
RAM usage: 1.60KiB (20.02%)
make[6]: Leaving directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/software/bios'
INFO:SoC:Initializing ROM rom with contents (Size: 0x62d4).
INFO:SoC:Auto-Resizing ROM rom from 0x20000 to 0x62d4.
make[6]: Entering directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/gateware'
symbiflow_synth -t digilent_arty -v /home/ggang/CFU-Playground/proj/proj_template/cfu.v /home/ggang/CFU-Playground/third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty.v -d artix7 -p xc7a35tcsg324-1 -x digilent_arty.xdc > /dev/null
symbiflow_pack -e digilent_arty.eblif -d xc7a50t_test -s digilent_arty.sdc > /dev/null
symbiflow_place -e digilent_arty.eblif -d xc7a50t_test -n digilent_arty.net -P xc7a35tcsg324-1 -s digilent_arty.sdc > /dev/null
Warning: IDELAY_GROUPS parameters are currently being ignored!
symbiflow_route -e digilent_arty.eblif -d xc7a50t_test -s digilent_arty.sdc > /dev/null
symbiflow_write_fasm -e digilent_arty.eblif -d xc7a50t_test > /dev/null
/home/ggang/CFU-Playground/env/symbiflow/bin/vpr_common: line 116: 73867 Killed genfasm ${ARCH_DEF} ${EBLIF} --device ${DEVICE_NAME} ${VPR_OPTIONS} --read_rr_graph ${RR_GRAPH} $@
make[6]: *** [Makefile:46: digilent_arty.fasm] Error 137
make[6]: Leaving directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/gateware'
Traceback (most recent call last):
File "./common_soc.py", line 57, in <module>
main()
File "./common_soc.py", line 53, in main
workflow.run()
File "/home/ggang/CFU-Playground/soc/board_specific_workflows/general.py", line 121, in run
soc_builder = self.build_soc(soc)
File "/home/ggang/CFU-Playground/soc/board_specific_workflows/digilent_arty.py", line 59, in build_soc
return super().build_soc(soc, **kwargs)
File "/home/ggang/CFU-Playground/soc/board_specific_workflows/general.py", line 98, in build_soc
soc_builder.build(run=self.args.build, **kwargs)
File "/home/ggang/CFU-Playground/third_party/python/litex/litex/soc/integration/builder.py", line 330, in build
vns = self.soc.build(build_dir=self.gateware_dir, **kwargs)
File "/home/ggang/CFU-Playground/third_party/python/litex/litex/soc/integration/soc.py", line 1139, in build
return self.platform.build(self, *args, **kwargs)
File "/home/ggang/CFU-Playground/third_party/python/litex/litex/build/xilinx/platform.py", line 55, in build
return self.toolchain.build(self, *args, **kwargs)
File "/home/ggang/CFU-Playground/third_party/python/litex/litex/build/xilinx/symbiflow.py", line 234, in build
_run_make()
File "/home/ggang/CFU-Playground/third_party/python/litex/litex/build/xilinx/symbiflow.py", line 84, in _run_make
raise OSError("Error occured during Symbiflow's script execution.")
OSError: Error occured during Symbiflow's script execution.
make[5]: *** [/home/ggang/CFU-Playground/soc/common_soc.mk:115: build/digilent_arty.proj_template/gateware/digilent_arty.bit] Error 1
make[5]: Leaving directory '/home/ggang/CFU-Playground/soc'
make[4]: *** [../proj.mk:287: bitstream] Error 2
make[4]: Leaving directory '/home/ggang/CFU-Playground/proj/proj_template'
ggang@ubuntu:~/CFU-Playground/proj/proj_template$
Hi @ggangliu , please follow these steps to get more information:
- Go to the build gateware directory:
cd /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/gateware
- In the
Makefile
, edit the linesymbiflow_write_fasm -e digilent_arty.eblif -d xc7a50t_test > /dev/null
to remove the> /dev/null
so that you can see the output. - Now (still in
gateware/
), just typemake
Hi @tcal-x, As you said, I got below logs, thanks.
I got below log if running “make” without "make clean".
ggang@ubuntu:~/CFU-Playground/soc/build/digilent_arty.proj_template/gateware$ make
make[2]: Entering directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/gateware'
symbiflow_write_bitstream -d artix7 -f digilent_arty.fasm -p xc7a35tcsg324-1 -b digilent_arty.bit
Writing bitstream ...
make[2]: Leaving directory '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_template/gateware'
ggang@ubuntu:~/CFU-Playground/soc/build/digilent_arty.proj_template/gateware$
But If I run "make clean" first, then to run "make", I got the log as attached file.
log.txt
Thanks @tcal-x I think I have knew the reason. I extended my virtual machine ram space to 3GB from 2GB, the issue was solved. Thanks a lot. All are because my personal fault.
@ggangliu thank you for your feedback. In fact I think I have an open issue -- that we need to print out a useful and informative error in this case (running out of memory). It is not your fault at all. The documentation does not even say "you should have X GB of memory available". So again, thank you for your feedback.
Also, there's a related topic -- we also don't currently print out an error if the place and route does not meet the timing constraints. In that case, the bitstream might not work on the board.