google / CFU-Playground

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM).

http://cfu-playground.rtfd.io/

google/CFU-Playground Issues

Program Not Working/Flashing On Tang Nano 9K
Updated 7 days ago4
Colab: Verilator compile in Conda env can't find the compiler
Updated 7 days ago6
Accuracy of perf_get_mcycle() or perf_get_mcycle64()
Updated 10 days ago14
Renode: cycles for a long-running CFU instruction are not tallied in $mcycle
Updated 15 days ago
Conda Symbiflow builds for Arty failing timing without warning?
Updated 15 days ago1
proj_template: make renode-headless fails
Updated 19 days ago5
hps_accel: make renode-headless fails with verilator error
Updated 19 days ago3
Specifying CPU variant in verilator
Closed 19 days ago1
ERROR: Can't load module `./dsp-ff'
Updated 20 days ago3
TFLite micro sync update is not correct; a moved file is now at both old and new locations.
Updated 21 days ago
LiteX / Verilator simulation doesn't work in Conda env; missing json_c/json.h, event2.listener.h
Updated 23 days ago
scripts/install_oxide failure: yosys plugins not built
Closed 24 days ago4
./scripts/install_oxide is broken (yosys plugin compilation)
Closed 25 days ago2
How to add a new board of FPGA device (alinx_ax7010)
Updated a month ago18
Basys3 board with Vivado gives error - memory region `main_ram' not declared
Updated a month ago1
Support 100T as variant of digilent_arty in makefiles
Closed a month ago2
Adding custom ML tflite models with CFU
Updated 2 months ago9
Add an XLS project
Updated 2 months ago
Allow target architecture primitive sim models in Verilator simulation
Updated 2 months ago
hps_accel in Renode fails the model golden tests
Closed 2 months ago1
Issue in code to use DSP-FF plugin
Closed 2 months ago
Trying different input for mnv2 model
Updated 2 months ago8
LiteX
Closed 2 months ago3
CFU Playground on Virtual machine
Updated 3 months ago3
Github action "oxide_fmax_fresh_build" is failing
Closed 3 months ago1
Turn off code sync workflows on forks.
Closed 3 months ago
Consider GDB support for CFU instructions via XML
Updated 3 months ago
Uprev yosys in CI to >= 0.10
Closed 3 months ago3
proj_template doesn't boot after "Liftoff" while LiteX demo does
Closed 4 months ago11
Try supporting nextpnr-xilinx
Closed 3 months ago1
Unable to load the RISCV program (Setup Guide) onto the board when using Symbiflow
Closed 3 months ago4
proj_template is not working
Updated 3 months ago6
hps_accel: max pool fails golden tests
Closed 3 months ago14
Building using "make -j2 software bitstream" results in an error
Updated 3 months ago
Add mlcommons test
Updated 3 months ago
Create a Personal Access Token for cfu-playground-bot
Closed 3 months ago4
Specialize amaranth code by platform
Updated 4 months ago
submodule pythondata_software_picolibc does not have a license
Updated 4 months ago2
Allow target frequency to be set/modified easily.
Closed 4 months ago1
got an issue in digilent_arty.fasm when building bitstream
Closed 4 months ago4
"make prog USE_SYMBIFLOW=1" ran into error
Updated 4 months ago5
Icestorm Package in Conda Environment
Closed 4 months ago3
How to use git@github.com protocal, because https is not stable for me
Closed 4 months ago3
cannot clone flashrom repo from google git
Closed 4 months ago2
gen2 CFU flakiness
Closed 5 months ago13
ERROR: Module `\FD' referenced in module `\digilent_arty' in cell `\FD_7' is not part of the design.
Closed 5 months ago5
hps_accel/gen2 gateware produces errors on FPGA
Closed 5 months ago2
VexRiscV - SlimoptCfu does not appear to be working
Updated 5 months ago13
Xilinx vivado log4j issue
Updated 5 months ago1
verilator sim with mport dual port arena
Updated 5 months ago

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