gdevic / A-Z80

An implementation of the Z80 CPU for Altera, Xilinx and Lattice FPGAs

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M1 asserted during bus acknowledge cycles

Noah1989 opened this issue · comments

It seems like the M1 signal is pulled low during bus acknowledge, which would break DMA to IO devices, since they could interpret the I/O request as an interrupt acknowledge. I have no original Z80 on hand right now, but I checked using Z80 explorer that M1 should indeed be high when BUSACK goes low.