Sound clock for APU frame counter wrong bits selected
maij opened this issue · comments
In the circuit diagram for timer module, the APU sound clock is derived from the DIV register bits 5 (4 MiHz clock) or 6 (8 MiHz clock), but these run at 256 Hz rather than the required 512 Hz. E.g. with an input clock of 4 MiHz (1 << 22) the 13th bit (DIV[5]) of the counter will divide this clock by 1 << (13 + 1), giving 1 << (22 - 14) = 1 << 8 = 256.
The correct bits for each speed mode should be DIV[4] (normal speed) and DIV[5] (double speed).
I think the error crept in because it's easy to miscount the frequency halving when 0-indexing.
https://gbdev.io/pandocs/Timer_Obscure_Behaviour.html#timer-global-circuit
Weird, I seem to remember DIV-APU events triggering at 256 Hz. Can we cite any source on that behaviour?
The section of the DIV-APU is correct AFAIK
Since that section was written referencing DMG-CPU-Inside, I think it's more trustworthy. Alright then, thank you!
Can you assign this issue to me and explain on what needs to be done ? @maij
Hi! Thanks for participating ^^
There are two ways to go about this.
- The simple way is to just edit the diagram so that the arrows coming from DIV's bits 5 and 6 come from bits 4 and 5 instead. (Preferably by moving everything they are connected to, as well.)
- The more involved way would be to convert those diagrams into SVGs, and make the correction in the new diagram. It would take more time, but would improve the docs more!
Regardless of which option you prefer, I'll remain available if you need any help.
Are you working on this @maij ?
No I'm not, feel free to go ahead.
Alright then, as per your request, I have assigned you to this issue!