Integrate the AXI Lite Ethernet Mac with the core

[fyquah]

Xilinx web pack does come with a free ethernet mac. The mac supports 100MB and 10MB ethernet, which is sufficient to get something working.

Implementing will comprises of a few steps:

1. Getting rid of the Tri_mode_ethernet module currently sitting in there
2. Wire up the AXI Ethernet lite mac, and expose the AXI lite ethernet interface directly.
3. Write an example that demonstrates (2)
4. Write a component that transforms the AXI Lite interface to the more ubiquitous AXI stream interface used in packet processing

[Eduard Silantyev]

Hi @fyquah

How would that approach be different from "Tri_mode_ethernet" approach? Also, by the module currently sitting there, are you referring to https://github.com/fyquah/hardcaml_arty/blob/master/examples/blinker/ips/hardcaml_arty_tri_mode_ethernet_mac_0/hardcaml_arty_tri_mode_ethernet_mac_0.xci?

On the same topic, I see that Ethernet section of the README is incomplete, could you share a basic example of using Ethernet with hardcaml on an Arty A7 board?

Ed