farzamgl

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

black-parrot

A Linux-capable host multicore for and by the world

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cva6-sdk

CVA6 SDK containing RISC-V tools and Buildroot

endoh1

Ascii Fluid Dynamics (not my code but a ioccc.org submission that is amazing)

fpnew

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Houseclub

A barebones unofficial Android app for Clubhouse

pynq_sd_images

riscv-gcc

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-linux

RISC-V Linux Port

riscv-pk

RISC-V Proxy Kernel

specstuff

verilator

Verilator open-source SystemVerilog simulator and lint system

zynq-farm