Han Bingjin's repositories
vexpparser
A Verilog Expression Parser Used for Assertions with Time Sensitivity
btor2verilog
Hacked together program to convert btor2 files to Verilog.
yosys_aiger
Convert Verilog to aiger format using yosys
RAG-system
Using LLM and RAG to build a Q-A system based on specific knowledge. GUI is implemented by Streamlit.
v-docs
verilog hdl
rtl_gate_sim_template
RTL-level and gate-level simulation Makefile templates using VCS and design compiler
vcs_template
VCS Makefile工程模板
elfread
读取elf文件信息
vcs_vscode_template
VCS+VScode远程开发工程模板
vcs_verdi_template
VCS+Verdi 的Makefile工程模板
MLX90640
The driver of MLX90604 for Arduino
digital-circuit
南京大学 计算机科学与技术系 数字逻辑与计算机组成 课程实验 https://nju-projectn.github.io/dlco-lecture-note/index.html
stAdv_pytorch
Spatially Transformed Adversarial Attack (PyTorch)
CRNN_STR
CRNN for Scene Text Recognition
FGSM-learn
Learn FGSM using PyTorch
mdpic-tools
Markdown Image tools using shell
lvgl
Powerful and easy-to-use embedded GUI library with many widgets, advanced visual effects (opacity, antialiasing, animations) and low memory requirements (16K RAM, 64K Flash).
Object-Detection
object detection using SSD Mobile Net v3
BadAppleOSC
在示波器上播放Bad Apple!!
SmallTools
Linux平台下的小工具
browserhome
My browser home page
CompressJPG
Using ImageMagick to compress JPG files
uvproj2make
convert keil project file(uvproj(x)) to make project(Makefile)