APU Tran Issues from ttlworks

Question

ogamespec opened this issue 2 years ago · comments

ogamespec · Answer 1 · Fri Jul 29 2022 16:36:23 GMT+0800 (China Standard Time)

ogamespec · Answer 2 · Fri Jul 29 2022 16:37:00 GMT+0800 (China Standard Time)

ogamespec · Answer 3 · Fri Jul 29 2022 16:37:23 GMT+0800 (China Standard Time)

EDIT: /ACLK4

ogamespec · Answer 4 · Fri Jul 29 2022 16:37:50 GMT+0800 (China Standard Time)

I don't see the problem, I've checked the topology and the transes 50 times.

EDIT: Actually... hehe

ogamespec · Answer 5 · Fri Jul 29 2022 16:38:13 GMT+0800 (China Standard Time)

APU > DPCM > frequency counter LFSR > order of Bits

Considering the wikipedia page about LFSRs,
for the DPCM frequency counter LFSR the naming order of Bits is swapped.

The LFSR Bit tied to the input feed should be named FR0 instead of FR8,
please check.

Note, that when changing the naming Bit order of the LFSR,
this also changes the naming Bit order of the DPCM decoder outputs.

ogamespec · Answer 6 · Fri Jul 29 2022 16:39:02 GMT+0800 (China Standard Time)

APU has a frequency LFSR in the DPCM section,
and a frequency LFSR in the Noise section.

Control signals for both LFSRs are labeled FLOAD,FSTEP in your schematics.
That might cause a problem to the "end user".

In my schematics, I now renamed the control signals for the DPCM frequency LFSR to DFLOAD,DFSTEP.

Please check.