emilgoh / mlp-xor

Hardware Implementation of Multi-Layer Perceptron with XOR Logic

Hardware Implementation of Multi-Layer Perceptron with XOR Logic

The Verilog code describes a multi-layer perceptron with pre-trained XOR logic weights and biases in the testbench.

Architecture of the MLP is as follow:

1. 2 Inputs
2. 1 Hidden Layer: 3 2-input neurons with ReLU activation function
3. 1 Output Layer: 1 output neuron with ReLU activation function

P.S. code is not optimised yet.