eiselekd

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Language:PythonApache-2.01314 59 948

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

Language:SystemVerilogApache-2.0979 34 42

duperemove

Tools for deduping file systems

Language:CGPL-2.0801 39 262

MoarVM

A VM with adaptive optimization and JIT compilation, built for Rakudo

Language:CNOASSERTION697 60 554

microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

Language:VerilogNOASSERTION654 41 71

llhd

Low Level Hardware Description — A foundation for building hardware design tools.

Language:RustApache-2.0392 26 139

bedup

Btrfs deduplication

Language:PythonGPL-2.0323 24 88

ghdl-yosys-plugin

VHDL synthesis (based on ghdl)

Language:VHDLGPL-3.0304 40 143

tendra

The TenDRA Project

Language:CNOASSERTION236 20 69

expandpass

Implements a simple nested grammar for expanding passwords

Language:C++161 12 5

meloader

Linux i386 tool to load and execute ME modules.

Language:C128 12 1

valentyusb

FPGA USB stack written in LiteX

Language:PythonBSD-3-Clause125 15 10

rakudo-and-nqp-internals-course

A course on Rakudo and NQP internals, developed by Edument AB.

Language:RakuNOASSERTION97 30 8

json

A tiny JSON parser and emitter for Perl 6 on Rakudo

Language:Perl 676 14 26

flexray-interceptor

FPGA project to man-in-the-middle attack Flexray

Language:VHDLMIT73 90

lambdavm

A programmable virtual CPU written in untyped lambda calculus

Language:Common LispMIT47 4 1

GAIA3

GAIA Processor

Language:VHDL25 40

litesata_axiom

Language:Python12 50

fpu

FPU written in VHDL

Language:VHDL8 50

Perl6-Renshu

Language:Raku500

GenesisOS

A learning project for osdev

Language:CGPL-3.02 10

fpu_in_c

Cでfpu書いたやつ

Language:C2 50

flexray-interceptor

FPGA project to man-in-the-middle attack Flexray

Language:VHDLMIT1 10