SD card digital recognition
KalyanOntipuli opened this issue · comments
The clk_div module is implemented by vivado IP Catalog Clocking Wizard (PLL) https://blog.csdn.net/baidu_25816669/article/details/88819916 (So the code in IP folder is generated by vivado automatically)
About: https://support.xilinx.com/s/question/0D52E00006iHlm5SAC/vivado-clock-ip-wizard?language=en_US
System clock (100Mhz) , is divided to 50MHz clock for sd card, 25MHz clock for vga.
@KalyanOntipuli The dual port ram mudule ram is also implemented by vivado IP Catalog block memory generate.
where i can find this coe file
This ram has no init data, it is for data cache(buffer)
plz send the constraints file
Sorry, I can not find it, it is so for from now... :(
The origin project was lost.
what are the port pins for input SD_CD , output SD_RESET , output SD_SCK , output SD_CMD output init_done_out, // SD initilization complete signal output [1:0] n_node, // number of vertical intersections output [1:0] m1_node_l, // the number of horizontal left intersection points output [1:0] m1_node_r, // the number of horizontal right intersection points output [1:0] m2_node_l, // the number of horizontal left intersection points output [1:0] m2_node_r, // the number of horizontal right intersection points
You can freely specify each port, our boards are not the same