dschaefer / fpga-template

Project template for FPGA dev

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Project template for FPGA Development

Supports building SystemVerilog for the ulx3s using open source tools yosys, nextpnr, and Project Trellis. Includes test support using verilator and googletest.

The example is a blinking LED which flashes around once a second.

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Project template for FPGA dev


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Language:SystemVerilog 78.0%Language:CMake 12.8%Language:C++ 8.2%Language:Shell 1.1%