user error: (Was: Multi-plane NAND support)
henrygab opened this issue · comments
My mistake .. I misread the datasheet to say that the planes were at the sector (aka page) level. They are at the block (aka "erase block") level. Thus, I think this is a non-issue. Keeping my old post as hidden details below.
old post -- my misunderstanding
I'm looking to use a dual-plane NAND chip (MT29F2G01ABAFDWB) with Dhara. This either needs a hack that is not preferable, or some adjustment for garbage collection in Dhara.
Multi-plane Background
See Page 11 of the datasheet for a decent figure.
As you likely know, with more than one plane, each plane has its own:
- pages
- cache register
- data register
For two planes, the plane is defined as (block_number % 2); For four planes, the plane is defined as (block_number % 4)`; etc. Thus, for two planes, all the even blocks are on one plane, and all the odd blocks are on the other plane.
When a page is erasable...
If I understand correctly, a page is erasable when all blocks in the plane are no longer actively in use. For code written only for single-plane NAND chips, all the blocks in a single page were sequentially numbered. This allowed detection of a page as "empty" when N consecutive pages(*) were empty, with N defined as the number of blocks in a page.
However, for two planes, that logic no longer holds... N consecutive pages would only fill half of a page on plane zero, and half of a page on plane one.
Potential Hack
My current thoughts are to "lie" to Dhara about the NAND, by reporting N * plane_count blocks per sector. As a result, Dhara should treat the page as being twice as large to support two planes.
Then, when Dhara then sends a request to erase a page, the NAND layer would have to erase multiple pages (one on each of the planes).
The downside to this, obviously, is that instead of a 128k page for garbage collection, Dhara must now find a 256k page (for two-plane) area that is empty (or to garbage-collect 256k), before it can erase a "page". While not technically a failure ... it's definitely sub-optimal behavior.
Two questions:
- Do you see any technical reason the above potential hack would fail to work?
- Would you have pointers for where in Dhara might need to be changed for native support of multiple planes? (I think it's just in the garbage collection?)
Of course, I welcome any other thoughts you might have on better ways to support this chip.
Thank you for any guidance you might offer!
(*) Yes, starting at a value divisible by N, so it's page aligned.