S Skandha Deepsita (deepsita)

deepsita

Geek Repo

Company:@IIITDMKancheepuram , @SMDP-C2SD MeitY

Location:Chennai

Home Page:https://www.linkedin.com/in/skandha-deepsita-sarvepalli-027433ba/

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S Skandha Deepsita's repositories

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VSD--Advanced-Physical-Design---OpenLane-SKY130

The step by step workflow for automation of RTL to GDSII using Sky-water PDK and open-source tool OpenLane.

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ACA-CSU_Approximate-Adders

MATLAB and HDL models of ACA-CSU approximate adders

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approx-fpgas

Approximate arithmetic circuits for FPGAs

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Approximate-Multipliers

Some verilog implentation on approximate circuits

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AXSOP

Energy Efficient Sum -of - Products Circuit

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caravel

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

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carry-cut-back-adder

Carry Cut-Back Adder (CCBA) - An approximate adder circuit with artificially-built false timing paths

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DeBAM_Decoder_based_Approximate_Multiplier

DeBAM : Decoder Based Approximate multiplier for Low Power Applications

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digital-flow

This is a tutorial on standard digital design flow

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evoapproxlib

Library of approximate arithmetic circuits

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Fixed2Float_MPW3

This project is the fixed point to floating point converter targetted for any DSP operations.

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Introduction-to-SoC-Design-Education-Kit

Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals

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P-DAC_INTERNSHIP

This project is design of 10-bit Potentiometric DAC with Sky-130 PDK

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Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

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riscduino

Arduino compatible Risc-V Based SOC

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spu32

Small Processing Unit 32: A compact RV32I CPU written in Verilog

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vsdBasicPD

Workshop on VLSI/SoC Physical Design concepts mapped with open source tools by VSD.

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yosys-als

A design space exploration tool for approximate circuits

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