darklife / darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

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Issue in LDATA

timdudu opened this issue · comments

In LDATA expression, when byte load(FCT3==0||FCT3==4), high bits should be ALL1[31:8]:ALL0[31:8], now it's ALL1[31:24]:ALL0[31:24].

thank you tim! you are right!