Tang Dongxue's repositories

riffa

The RIFFA development repository

License:NOASSERTIONStargazers:0Issues:0Issues:0

OpenCV-Python-Tutorial

📖 OpenCV-Python image processing tutorial for beginners

Stargazers:0Issues:0Issues:0

pycharmproj

pychram github test

Language:PythonStargazers:0Issues:0Issues:0
License:MITStargazers:0Issues:0Issues:0

Python

All Algorithms implemented in Python

License:MITStargazers:0Issues:0Issues:0

sm64

A Super Mario 64 decompilation, brought to you by a bunch of clever folks.

Stargazers:0Issues:0Issues:0

UXE-Use-Experience

record the experience of using the UXE Tool

Language:VHDLLicense:GPL-3.0Stargazers:1Issues:0Issues:0

keras-yolo3

A Keras implementation of YOLOv3 (Tensorflow backend)

License:MITStargazers:0Issues:0Issues:0

hls4ml

Machine learning in FPGAs using HLS

License:Apache-2.0Stargazers:0Issues:0Issues:0

verilog-axis

Verilog AXI stream components for FPGA implementation

License:MITStargazers:0Issues:0Issues:0

wujian100_open

IC design and development should be faster,simpler and more reliable

License:MITStargazers:1Issues:0Issues:0

lc-all-solutions

My own leetcode solutions by python

Stargazers:0Issues:0Issues:0
License:NOASSERTIONStargazers:0Issues:0Issues:0

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

License:Apache-2.0Stargazers:1Issues:0Issues:0

HarmonyOS

A curated list of awesome things related to HarmonyOS. 华为鸿蒙操作系统。

Language:CStargazers:0Issues:0Issues:0

SublimeLinter-contrib-verilator

👌 This linter plugin for SublimeLinter provides an interface to Verilator (Verilog Simulator)

License:MITStargazers:0Issues:0Issues:0

myhdl

The MyHDL development repository

Language:PythonLicense:LGPL-2.1Stargazers:0Issues:0Issues:0

Verilog-Gadget

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

Stargazers:0Issues:0Issues:0

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

Language:VerilogStargazers:0Issues:0Issues:0

mindMap

the mind maps used to record of personal reading or thinking

License:MITStargazers:0Issues:0Issues:0

gen_amba

AMBA bus generator including AXI, AHB, and APB

Stargazers:0Issues:0Issues:0

tesseract

Tesseract Open Source OCR Engine (main repository)

Language:C++License:Apache-2.0Stargazers:0Issues:0Issues:0

SmallSolvedProblem

note the problems happened when use software or system

Stargazers:0Issues:0Issues:0

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

Language:AssemblyLicense:MITStargazers:0Issues:0Issues:0

myhdl-resources

A collection of awesome MyHDL tutorials, projects and third-party tools.

Stargazers:0Issues:0Issues:0

CSI2Rx

Open Source 4k CSI-2 Rx core for Xilinx FPGAs

Language:VHDLLicense:MITStargazers:0Issues:0Issues:0

SDSOC_CV_ML

SDSoC, Computer Vision and Machine Learning

Language:MakefileStargazers:0Issues:0Issues:0

ML_Embedded_Workshop

Machine Language workshop for XDF

Stargazers:0Issues:0Issues:0

HLx_Examples

Open Source HLx Examples

Language:MatlabLicense:BSD-3-ClauseStargazers:0Issues:0Issues:0

fpga-virtual-console

VT220-compatible console on Cyclone IV EP4CE55F23I7

License:GPL-3.0Stargazers:1Issues:0Issues:0