cisen's repositories
fpga-drive-aximm-pcie
Example designs for FPGA Drive FMC
4_bit_RPN_Calculator
A multisim project using counters, multiplexers, RAM chips, and ALUs to create an RPN calculator
artix-dc-scm
Experimental Xilinx Artix-7 driven Data Center Security Communication Module
chisel-tutorial
chisel tutorial exercises and answers
Cores-SweRV-EL2
SweRV EL2 Core
cpp-cmake-template-cpp11
Template project for C++ and C projects built with CMake using GCC or LLVM
e203_hbirdv2
The Ultra-Low Power RISC-V Core
edifier-flex-rust
Like an emulsifier, edifier aims to allow you to mix rust and edif.
freedom
Source files for SiFive's Freedom platforms
jfpjc
John's Field-Programmable JPEG Compressor; a jpeg compressor written in verilog. Currently targeted to deploy to Lattice's iCE40 up5k fpga.
Limago
Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
lpddr4-test-board
Experimental development board interfacing Xilinx Kintex-7 FPGA with LPDDR4 SDRAM
MetaSys
Metasys is the first open-source FPGA-based infrastructure with a prototype in a RISC-V core, to enable the rapid implementation and evaluation of a wide range of cross-layer software/hardware cooperative techniques techniques in real hardware. Described in our pre-print: https://arxiv.org/abs/2105.08123
PAAS_V1.0
PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
Quasar
Quasar 2.0: Chisel equivalent of SweRV-EL2
riscv-starship
Run rocket-chip on FPGA
rocket-system
Custom top for the Rocket Chip
soucecode-cache-simulation
SystemVerilog cache simulation
SynologySsoDemo
群晖sso 单点登录开发
vite
Next generation frontend tooling. It's fast!
xfcp
Extensible FPGA control platform