cisen's repositories

flex-bison-rust

Santiago is a lexing and parsing toolkit for Rust

Language:RustStargazers:3Issues:0Issues:0

Colorlight-FPGA-Projects

current focus on Colorlight i5 and i9 module

License:Apache-2.0Stargazers:0Issues:0Issues:0

Cores-SweRV

SweRV EH1 core

License:Apache-2.0Stargazers:0Issues:0Issues:0

EDA-wiki

EDA wiki

Stargazers:0Issues:0Issues:0

FPGA-USB-Device

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

Stargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0

Light-HLS-xilinx-vivado-fpga-llvm

Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)

Language:C++License:GPL-3.0Stargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0

llvm-ir-tutorial-rust

LLVM IR入门指南

Stargazers:0Issues:0Issues:0

lowcode-engine

An enterprise-class low-code technology stack with scale-out design / 一套面向扩展设计的企业级低代码技术体系

License:MITStargazers:0Issues:0Issues:0

lowcode-engine-ext

An enterprise-class low-code technology stack with scale-out design / 一套面向扩展设计的企业级低代码技术体系

Language:TypeScriptLicense:MITStargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0

nano-cpu32k

Superscalar out-of-order RISC core (with Cache& MMU) and SoC, supporting GNU toolchain & Linux 4.20 kernel, having been verified on Xilinx Kintex-7 FPGA.

License:NOASSERTIONStargazers:0Issues:0Issues:0

noxueui

不学网前端,rust+yew开发

Stargazers:0Issues:0Issues:0

open-nic-shell

OpenNIC Shell includes the HDL source files

License:Apache-2.0Stargazers:0Issues:0Issues:0
Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0

PDFPatcher

PDF补丁丁

Language:C#Stargazers:0Issues:0Issues:0

platform-chipsalliance

CHIPS Alliance: development platform for PlatformIO

License:Apache-2.0Stargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0

RFSoC_Controller_V2-FIFO

Version 2 of RFSoC_Controller

Stargazers:0Issues:0Issues:0

Rift2Core

Based on Chisel3, Rift2Core is a 9-stage, out-of-orde,r 64-bits RISC-V Core, which supports RV64GC.

Language:ScalaLicense:Apache-2.0Stargazers:0Issues:0Issues:0
Language:VHDLStargazers:0Issues:0Issues:0

rust-jtag

JTAG abstraction library for Rust

Language:RustLicense:0BSDStargazers:0Issues:0Issues:0

sourcecode-SimpleCache

Simple cache design implementation in verilog

Language:VerilogLicense:MITStargazers:0Issues:0Issues:0

SVG-Loaders

Loading icons and small animations built with pure SVG.

Language:HTMLLicense:MITStargazers:0Issues:0Issues:0

SweRV_FPGA

SweRV FPGA design of Vivado

Stargazers:0Issues:0Issues:0
License:NOASSERTIONStargazers:0Issues:0Issues:0

wujian100_open

IC design and development should be faster,simpler and more reliable

Language:VerilogLicense:MITStargazers:0Issues:0Issues:0
Language:PythonLicense:NOASSERTIONStargazers:0Issues:0Issues:0