chinamaoge's starred repositories
zju-icicles
浙江大学课程攻略共享计划
编程电子书，电子书，编程书籍，包括C，C#，Docker，Elasticsearch，Git，Hadoop，HeadFirst，Java，Javascript，jvm，Kafka，Linux，Maven，MongoDB，MyBatis，MySQL，Netty，Nginx，Python，RabbitMQ，Redis，Scala，Solr，Spark，Spring，SpringBoot，SpringCloud，TCPIP，Tomcat，Zookeeper，人工智能，大数据类，并发编程，数据库类，数据挖掘，新面试题，架构设计，算法系列，计算机类，设计模式，软件测试，重构优化，等更多分类
baidu-netdisk-downloaderx
⚡️ 一款图形界面的百度网盘不限速下载器，支持 Windows、Linux 和 Mac。
Reinforcement-learning-with-tensorflow
Simple Reinforcement learning tutorials, 莫烦Python 中文AI教学
xv6-public
xv6 OS
ipv6-hosts
Fork of https://code.google.com/archive/p/ipv6-hosts/, focusing on automation
biaxial-rnn-music-composition
A recurrent neural network designed to generate classical music.
ChineseCodingInterviewAppendix
The source code for the appendix part of the Chinese version of the book Coding Interviews
linux-xlnx
The official Linux kernel from Xilinx
RX-Explorer
一款优雅的UWP文件管理器 | An elegant UWP Explorer
xilinx_axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
QtTcpThreadServer
QtTcpThreadServer
RNN-TrajModel
The source of the IJCAI2017 paper "Modeling Trajectory with Recurrent Neural Networks"
zynq-axi-dma-sg
Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020
FUI-Audio-DAC
FPGA-Based USB-Input Audio Digital to Analogue Converter
fpga_dac
Project which creates an analogic sine signal from an architecture that involves FPGA. It were used a DDS core to generate the sine and SPI communication to control DAC conversor (AD5791 Analog Devices). To choose the sine frequency and the update frequency of a new data we developed a cpp application. The "documentation" folder has more details of the project, including datasheets, state machine and block diagram.
WinTcpServer
一个简单的基于 windows API 的 TCP Server
Implementation-of-Simplified-TCP-using-the-NIOS-II-in-Intel-DE2i-150-FPGA-board.
Created Qsys system that includes Nios II, Triple-Speed Ethernet IP Core, SGDMA controller and other hardware components for transmit and receive operation. Two Phase-Locked Loop modules are added to the design to generate clocks with different frequencies to make the Triple-Speed Ethernet system (which implements the MAC function) work properly at 10/100/1000 Mbps. After building the hardware system and downloading the circuit onto the FPGA, run an application program written in C language. Based on the inputs from the board it establishes and closes the TCP connection, transmit and receive data frames from the Ethernet port of the board. Ethernet frames are transmitted based on Stop and Wait Protocol and Altera Timer core is added to re-transmit frames after Timeout.
iio_dac7750
Linux IIO driver for Texas Instruments DAC7750 12-Bit SPI DAC