Brian Padalino's repositories
vhdl-format
VHDL String Formatting Library
sublime-hdl
HDL support for Sublime Text 2
Verilog.tmbundle
Verilog TextMate Bundle
vhdl-ideas
VHDL-2019 Ideas and Utilities
cifra
A collection of cryptographic primitives targeted at embedded use.
Compliance-Tests
Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
fpga
The USRP™ Hardware Driver FPGA Repository
gr-ettus
Out-of-tree GNU Radio Module for Experimental Ettus Research Features
hdl
HDL libraries and projects
Interfaces
Interface definitions for VHDL-2019.
nvc
VHDL compiler and simulator
OSVVM-Scripts
OSVVM project simulation scripts. Scripts are tedious. These scripts simplify the steps to compile your project for simulation
pyVHDLParser
Streaming based VHDL parser.
rust_hdl_vscode
VHDL Language Support for VSCode
uhd
The USRP™ Hardware Driver Repository
vhdl-style-guide
Style guide enforcement for VHDL
vhdl.tmbundle
TextMate support for VHDL