bolifeyo

bolifeyo

Geek Repo

0

following

0

stars

Github PK Tool:Github PK Tool

bolifeyo's repositories

AdderNet

Code for paper " AdderNet: Do We Really Need Multiplications in Deep Learning?"

Language:PythonLicense:BSD-3-ClauseStargazers:0Issues:0Issues:0

ARM_AMBA_Design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

Language:VerilogLicense:GPL-3.0Stargazers:0Issues:0Issues:0

cmake-examples

Useful CMake Examples

Language:CMakeLicense:MITStargazers:0Issues:0Issues:0

Computer-Architecture

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

Language:VerilogStargazers:0Issues:0Issues:0

darknet_ros

YOLO ROS: Real-Time Object Detection for ROS

License:BSD-3-ClauseStargazers:0Issues:0Issues:0

Data-Structures-and-Algorithms-Python

All the essential resources and template code needed to understand and practice data structures and algorithms in python with few small projects to demonstrate their practical application.

Stargazers:0Issues:0Issues:0

databook_python

IPython notebooks with demo code intended as a companion to the book "Data-Driven Science and Engineering: Machine Learning, Dynamical Systems, and Control" by Steven L. Brunton and J. Nathan Kutz

Stargazers:0Issues:0Issues:0

deep_sort_pytorch

MOT tracking using deepsort and yolov3 with pytorch

License:MITStargazers:0Issues:0Issues:0

EmojiRecommend

소웨지존 팀, 이모티콘 추천 분류기 (2019)

License:MITStargazers:0Issues:0Issues:0

FKP

Official PyTorch code for Flow-based Kernel Prior with Application to Blind Super-Resolution (FKP), CVPR2021

License:Apache-2.0Stargazers:0Issues:0Issues:0

Hazard3

3-stage RV32IMACZb* processor with debug

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0

hf-risc

HF-RISC SoC

License:GPL-2.0Stargazers:0Issues:0Issues:0

kronos

Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations

License:Apache-2.0Stargazers:0Issues:0Issues:0

libtorch-yolov5

A LibTorch inference implementation of the yolov5

License:MITStargazers:0Issues:0Issues:0

mmRISC-1

RISC-V RV32IMAFC Core for MCU

License:BSD-2-ClauseStargazers:0Issues:0Issues:0

ModooCode

Repo for the Modoocode.

License:Apache-2.0Stargazers:0Issues:0Issues:0

nvdla-parser

A NVDLA Loadable Parser.

Stargazers:0Issues:0Issues:0

Pruned-YOLO

Using model pruning method to obtain compact models Pruned-YOLOv5 based on YOLOv5.

Language:PythonLicense:Apache-2.0Stargazers:0Issues:0Issues:0

Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

License:MITStargazers:0Issues:0Issues:0

riscv-simple

Computer architecture learning environment using FPGAs

License:NOASSERTIONStargazers:0Issues:0Issues:0

riscv-simple-sv

A simple RISC V core for teaching

Language:SystemVerilogLicense:BSD-3-ClauseStargazers:0Issues:0Issues:0

riscv-z0

RISC-V Z0 - A RISCV32-IMC CORE

License:Apache-2.0Stargazers:0Issues:0Issues:0

riscv-z1

RISC-V Z1 - A RISCV32-IMCB CORE

License:Apache-2.0Stargazers:0Issues:0Issues:0

riscv-z3

RISC-V Z3 - A RISCV32-IMCB CORE

License:Apache-2.0Stargazers:0Issues:0Issues:0

wb2axip

Bus bridges and other odds and ends

Language:VerilogStargazers:0Issues:0Issues:0

yolov5

YOLOv5 🚀 in PyTorch > ONNX > CoreML > TFLite

Language:PythonLicense:GPL-3.0Stargazers:0Issues:0Issues:0
Stargazers:0Issues:0Issues:0

Yolov5_DeepSort_Pytorch

Real-time multi-object tracker using YOLO v5 and deep sort

License:GPL-3.0Stargazers:0Issues:0Issues:0

YoloV5sl_V4_prune

YoloV5sl_V4模型pruning

License:Apache-2.0Stargazers:0Issues:0Issues:0

ZYNQ-NVDLA

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

Stargazers:0Issues:0Issues:0