Redundant Net/Reg Redeclaration

[Andrew Whigham]

Currently output ports are converted to wire (if the original is just output) or reg (if the original is output reg) during the inlining process in the method Inliner._instantiation_to_inlined_body. This is done through a simple find and replace mechanism. However, this in Verilog it is typical, though not required, to declare and output and a reg of the same name (which hold the same values). For example:

module Foo;
    output bar;
    reg bar;
    //Code
endmodule;

When this is inlined from its instantiation by the aforementioned method, it will have a declaration of a wire bar and reg bar, which is incorrect. Only the latter declaration should be present.

One solution to this could be creating a new data member within the Module object to store a list of all regs and wires within the module. Alternatively a similar check could be performed at the time an output port is converted.