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Yale Asynchronous VLSI and Architecture Group (asyncvlsi)

Yale Asynchronous VLSI and Architecture Group

asyncvlsi

Geek Repo

Research group led by Rajit Manohar working on asynchronous digital circuits and systems

Home Page:http://avlsi.csl.yale.edu/

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Yale Asynchronous VLSI and Architecture Group's repositories

act

ACT hardware description language and core tools.

Language:C++License:GPL-2.0Stargazers:95Issues:15Issues:24

SPRoute

A parallel global router using the Galois framework

Language:C++License:NOASSERTIONStargazers:25Issues:4Issues:1

actflow

Top-level repository for the ACT EDA flow

Language:ShellLicense:GPL-2.0Stargazers:22Issues:1Issues:2

summer2022

Summer School Week 1 & 2 repo

Language:ShellLicense:GPL-2.0Stargazers:11Issues:5Issues:0

chp2prs

Automated conversion from CHP to PRS using syntax-directed translation

Language:C++License:GPL-2.0Stargazers:7Issues:9Issues:11

interact

Command-line design environment for asynchronous logic

Language:C++License:GPL-2.0Stargazers:6Issues:5Issues:4

stdlib

ACT standard library

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phyDB

Library that holds the physical database

Language:C++License:LGPL-2.1Stargazers:5Issues:3Issues:0

actsim

Language:C++License:GPL-2.0Stargazers:4Issues:2Issues:0

Dali

A gridded cell placer

Language:C++License:GPL-2.0Stargazers:4Issues:5Issues:2

PWRoute

Power and ground routing

Language:C++License:LGPL-2.1Stargazers:3Issues:3Issues:0

xcell

Cell library characterizer

Language:C++License:GPL-2.0Stargazers:3Issues:2Issues:1

ACT-editor

Eclipse environment for ACT

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prs2fpga

Translate production rules into Verilog for accelerated simulation on FPGAs

Language:C++License:GPL-2.0Stargazers:2Issues:1Issues:0

dflowmap

Convert ACT dataflow to simulatable ACT CHP

Language:C++License:GPL-2.0Stargazers:1Issues:3Issues:3

tracelib

Trace file library interface for creating simulation traces in a range of formats

Language:CLicense:LGPL-2.1Stargazers:1Issues:1Issues:0

TritonRoute-WXL

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Xyce

The Xyce™ Parallel Electronic Simulator

Language:CLicense:GPL-3.0Stargazers:1Issues:1Issues:0

actpass

Example template for a dynamically loaded analysis/transformation pass for ACT

Language:CLicense:Apache-2.0Stargazers:0Issues:1Issues:0

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

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BiPart

Parallel hypergraph partitioner

Language:C++License:LGPL-2.1Stargazers:0Issues:3Issues:0

dflow2dot

Visualize an ACT dataflow graph

Language:C++License:GPL-2.0Stargazers:0Issues:1Issues:0

expropt

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irsim

IRSIM switch-level simulator for digital circuits

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layout

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magic

Magic VLSI Layout Tool

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ocaml_act

OCaml front-end for ACT

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sky130l

ACT configuration files for Skywater 130nm using teaching-friendly lambda rules

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utils

Miscellaneous scripts/utilities to be used with the ACT flow

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xyce_build

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