Asim Ahsan's repositories
Digital-Systems-Labs
Fall 2016 EE 460M Digital Systems Using HDL Lab Assignments
2D-convolution-on-FPGA
Implemented a custom-IP 2D convolution block for Xilinx Zedboard Zynq-7000 FPGA using synthesizable System Verilog in Vivado
asimahsan1990
Config files for my GitHub profile.
count-dorakula
Simple counter for blood donor event in Fasilkom UI.
csmith
Csmith, a random generator of C programs
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
deep-learning-coursera
Deep Learning Specialization by Andrew Ng on Coursera.
exams
Past Exams for UC Berkeley EECS Courses. PR more if you have!
Hardware-CNN
A convolutional neural network implemented in hardware (verilog)
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Image-Processing-Pipeline
Image processing operations in System Verilog and C. Functional.
lab_10
final_code
lenet5_hls
FPGA Accelerator for CNN using Vivado HLS
openISP
Image Signal Processor
ParCNN
A hardware implementation of a parametric convolutional neural network
psx-data-reader
A scraper for downloading Pakistan stock exchange's data into Python Pandas DataFrame.
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
sobel
Implementation of Sobel Filter in Verilog